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19-4630; Rev 0; 7/09
KIT ATION EVALU E AILABL AV
Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs
Features
Excellent Dynamic Performance 69.9dB SNR at 5.3MHz 94dBc SFDR at 5.3MHz Ultra-Low Power 114mW per Channel (Normal Operation) Serial LVDS Outputs Pin-Selectable LVDS/SLVS (Scalable Low-Voltage Signal) Mode LVDS Outputs Support Up to 30in FR4 Backplane Connections Test Mode for Digital Signal Integrity Fully Differential Analog Inputs Wide Differential Input Voltage Range (1.4VP-P) On-Chip 1.24V Precision Bandgap Reference Clock Duty-Cycle Equalizer Compact, 68-Pin Thin QFN Package with Exposed Pad Evaluation Kit Available (Order MAX1437BEVKIT)
General Description
The MAX1438B octal, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. This ADC is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. The MAX1438B operates from a 1.8V single supply and consumes only 913mW (114mW per channel) while delivering a 69.9dB (typ) signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1438B features a lowpower standby mode for idle periods. An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise. A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip phase-locked loop (PLL) generates the high-speed serial low-voltage differential signal (LVDS) clock. The MAX1438B has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two's-complement format. The MAX1438B offers a maximum sample rate of 64Msps. This device is available in a small, 10mm x 10mm x 0.8mm, 68-pin thin QFN package with exposed pad and is specified for the extended industrial (-40C to +85C) temperature range.
MAX1438B
Ordering Information
PART MAX1438BETK+ TEMP RANGE -40C to +85C PIN-PACKAGE 68 Thin QFN-EP*
Applications
Ultrasound and Medical Imaging Instrumentation Multichannel Communications
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
ABSOLUTE MAXIMUM RATINGS
AVDD to GND........................................................-0.3V to +2.0V CVDD to GND........................................................-0.3V to +3.6V OVDD to GND .......................................................-0.3V to +2.0V IN_P, IN_N to GND .................................-0.3V to (VAVDD + 0.3V) CLK to GND ...........................................-0.3V to (VCVDD + 0.3V) OUT_P, OUT_N, FRAME_, CLKOUT_ to GND ..............................-0.3V to (VOVDD + 0.3V) DT, SLVS/LVDS, LVDSTEST, PLL_, STBY REFIO, REFADJ, CMOUT to GND......-0.3V to (VAVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 68-Pin Thin QFN, 10mm x 10mm x 0.8mm (derate 70mW/C above +70C) ................................4000mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, external VREFIO = 1.24V, CREFIO to GND = 0.1F || 1.0F, CREFP to GND = 10F, CREFN to GND = 10F, fCLK = 64MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY (Note 2) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUTS (IN_P, IN_N) Input Differential Range Common-Mode Voltage Range Common-Mode Voltage Range Tolerance Differential Input Impedance Differential Input Capacitance CONVERSION RATE Maximum Conversion Rate Minimum Conversion Rate Data Latency DYNAMIC CHARACTERISTICS (Differential Inputs, 4096-Point FFT) (Note 2) Signal-to-Noise Ratio Signal-to-Noise and Distortion Effective Number of Bits Spurious-Free Dynamic Range SNR SINAD ENOB SFDR fIN = 5.3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS 79 10.8 67 67 69.9 69.6 69.8 69.6 11.4 11.4 94 93 dB dB Bits dBc fSMAX fSMIN 64 4.0 6.5 MHz MHz Cycles RIN CIN VID VCMO (Note 3) Switched capacitor load Differential input 1.4 0.76 50 2 12.5 VP-P V mV k pF -3 0.5 N INL DNL No missing codes over temperature 12 0.4 0.25 2.5 1 0.5 +2 Bits LSB LSB %FS %FS SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V , external VREFIO = 1.24V, CREFIO to GND = 0.1F || 1.0F, CREFP to GND = 10F, CREFN to GND = 10F, fCLK = 64MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Total Harmonic Distortion Intermodulation Distortion Third-Order Intermodulation Aperture Jitter Aperture Delay Small-Signal Bandwidth Full-Power Bandwidth Output Noise Overrange Recovery Time INTERNAL REFERENCE REFADJ Internal Reference-Mode Enable Voltage REFADJ Low-Leakage Current REFIO Output Voltage Reference Temperature Coefficient EXTERNAL REFERENCE REFADJ External ReferenceMode Enable Voltage REFADJ High-Leakage Current REFIO Input Voltage REFIO Input Voltage Tolerance REFIO Input Current CMOUT Output Voltage CLOCK INPUT (CLK) Input High Voltage Input Low Voltage Clock Duty Cycle Clock Duty-Cycle Tolerance Input Leakage Input Capacitance DIIN DCIN Input at GND Input at VAVDD 5 VCLKH VCLKL 50 30 5 80 0.8 x VAVDD 0.2 x VAVDD V V % % A pF IREFIO VCMOUT COMMON-MODE OUTPUT (CMOUT) 0.76 V (Note 4) VAVDD 0.1V 200 1.24 5 <1 V A V % A VREFIO TCREFIO 1.18 (Note 4) 1.5 1.24 120 1.30 0.1 V mA V ppm/C tOR SYMBOL THD IMD IM3 tAJ tAD SSBW LSBW CONDITIONS fIN = 5.3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS f1 = 5.3MHz at -6.5dBFS f2 = 6.3MHz at -6.5dBFS f1 = 5.3MHz at -6.5dBFS f2 = 6.3MHz at -6.5dBFS Figure 10 Figure 10 Input at -20dBFS Input at -0.5dBFS IN_P = IN_N RS = 25, CS = 50pF MIN TYP -95 -92 89.3 97.5 < 0.4 1 100 100 0.44 1 -79 MAX UNITS dBc dBc dBc psRMS ns MHz MHz LSBRMS Clock cycle
MAX1438B
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3
Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, external VREFIO = 1.24V, CREFIO to GND = 0.1F || 1.0F, CREFP to GND = 10F, CREFN to GND = 10F, fCLK = 64MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN 0.8 x VAVDD 0.2 x VAVDD Input at GND Input at VAVDD 5 RTERM = 100 RTERM = 100 RTERM = 100, CLOAD = 5pF RTERM = 100, CLOAD = 5pF RTERM = 100 RTERM = 100 RTERM = 100, CLOAD = 5pF RTERM = 100, CLOAD = 5pF 250 1.125 350 350 205 220 320 320 200 60 1.7 1.7 1.7 STBY = 0, DT = 0 AVDD Supply Current IAVDD fIN = 20MHz at -0.5dBFS STBY = 0, DT = 1 STBY = 1, no clock input STBY = 0 OVDD Supply Current IOVDD fIN = 20MHz at -0.5dBFS STBY = 0, DT = 1 STBY = 1, no clock input CVDD Supply Current Power Dissipation ICVDD PDISS CVDD is used only to bias ESD-protection diodes on CLK input, Figure 2 fIN = 20MHz at -0.5dBFS 1.8 1.8 1.8 422 422 37 85 85 16 0 913 1035 110 mA A mA mW 1.9 1.9 3.5 465 mA 450 1.375 5 80 TYP MAX UNITS
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, STBY) Input High Threshold Input Low Threshold Input Leakage Input Capacitance Differential Output Voltage Output Common-Mode Voltage Rise Time (20% to 80%) Fall Time (80% to 20%) Differential Output Voltage Output Common-Mode Voltage Rise Time (20% to 80%) Fall Time (80% to 20%) STANDBY MODE (STBY) STBY Fall to Output Enable STBY Rise to Output Disable POWER REQUIREMENTS AVDD Supply Voltage Range OVDD Supply Voltage Range CVDD Supply Voltage Range VAVDD VOVDD VCVDD V V V tENABLE tDISABLE s ns VIH VIL DIIN DCIN VOHDIFF VOCM tRL tFL VOHDIFF VOCM tRS tFS V V A pF mV V ps ps mV mV ps ps
LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
4
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, external VREFIO = 1.24V, CREFIO to GND = 0.1F || 1.0F, CREFP to GND = 10F, CREFN to GND = 10F, fCLK = 64MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN (tSAMPLE/24) - 0.15 TYP MAX (tSAMPLE/24) + 0.15 UNITS
MAX1438B
TIMING CHARACTERISTICS (Note 5) Data Valid to CLKOUT Rise/Fall CLKOUT Output-Width High CLKOUT Output-Width Low FRAME Rise to CLKOUT Rise Sample CLK Rise to FRAME Rise Crosstalk Gain Matching Phase Matching CGM CPM tOD tCH tCL tCF tSF Figure 5 (Note 6) Figure 5 Figure 5 Figure 4 (Note 6) Figure 4 (Note 6) (Note 2) fIN = 5.3MHz (Note 2) fIN = 5.3MHz (Note 2) ns ns ns ns ns dB dB Degrees
tSAMPLE/12 tSAMPLE/12 (tSAMPLE/24) - 0.15 (tSAMPLE/2) + 1.1 -73 0.1 0.25 (tSAMPLE/24) + 0.15 (tSAMPLE/2) + 2.6
Note 1: Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design and characterization and not subject to production testing. Note 2: See definition in the Parameter Definitions section at the end of this data sheet. Note 3: See the Common-Mode Output (CMOUT) section. Note 4: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the internal bandgap reference and enable external reference mode. Note 5: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level. Note 6: Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 64MHz (50% duty cycle), DT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
FFT PLOT (16,384-POINT DATA RECORD)
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 20 FREQUENCY (MHz) 25 30
HD2 HD3
MAX1438B toc01
FFT PLOT (16,384-POINT DATA RECORD)
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 20 FREQUENCY (MHz) 25 30
HD2 HD3
MAX1438B toc02
CROSSTALK (16,384-POINT DATA RECORD)
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 20 FREQUENCY (MHz) 25 30
MAX1438B toc03
fCLK = 64.0000006MHz fIN = 5.3164063MHz AIN = -0.5dBFS SNR = 69.881dB SINAD = 69.874dB THD = -101.811dB SFDR = 100.723dB
fCLK = 64.0000001MHz fIN = 30.3007813MHz AIN = -0.5dBFS SNR = 69.609dB SINAD = 69.585dB THD = -92.323dBc SFDR = -92.870dBc
MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 2 fIN(N1) = 5.3164063MHz fIN(N2) = 30.3007813MHz CROSSTALK = -72.5dB fIN(N2)
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5
Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
Typical Operating Characteristics (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 64MHz (50% duty cycle), DT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
TWO-TONE INTERMODULATION DISTORTION (16,384-POINT DATA RECORD)
MAX1438B toc04
BANDWIDTH vs. ANALOG INPUT FREQUENCY
MAX1438B toc05
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1438B toc06
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 20 25 30 FREQUENCY (MHz) fIN(IN1) = 5.296593MHz fIN(IN2) = 6.299991MHz AIN1 = -6.5dBFS AIN2 = -6.5dBFS IMD = 89.3dBc IM3 = 97.5dBc
2 1 0 -1 -2 GAIN (dB) -3 -4 -5 -6 -7 -8 -9 -10 1 10
FULL-POWER BANDWIDTH -0.5dBFS
72 71 70 SNR (dB)
SMALL-SIGNAL BANDWIDTH -20.5dBFS
69 68 67 66 65 0 20 40 60 fIN (MHz) 80 100 120
100
1000
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1438B toc07
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1438B toc08
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
100 95
MAX1438B toc09
72 71 70 SINAD (dB) 69 68 67 66 65 0 20 40 60 fIN (MHz) 80 100
-80 -85 -90
105
SFDR (dBc)
THD (dBc)
90 85 80 75
-95 -100 -105 -110
70 65 0 20 40 60 fIN (MHz) 80 100 120 0 20 40 60 fIN (MHz) 80 100 120
120
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER
MAX1438B toc10
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER
MAX1438B toc11
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER
-60 -65 -70 THD (dBc) -75 -80 -85 -90 -95 -100 -105 fIN = 5.3037109MHz
MAX1438B toc12
75 fIN = 5.3037109MHz 70 65
75 fIN = 5.3037109MHz 70 65 SINAD (dB) 60 55 50 45 40 35
-55
SNR (dB)
60 55 50 45 40 35 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dBFS)
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
6
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs
Typical Operating Characteristics (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 64MHz (50% duty cycle), DT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER
MAX1438B toc13
MAX1438B
SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE
MAX1438B toc14
SIGNAL-TO-NOISE PLUS DISTORTION vs. SAMPLING RATE
fIN = 5.3037109MHz 73 72 SINAD (dB) 71 70 69 68 67 66
MAX1438B toc15
105 100 95 90 SFDR (dBc) 85 80 75 70 65 60 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dBFS) fIN = 5.3037109MHz
74 fIN = 5.3037109MHz 73 72 SNR (dB) 71 70 69 68 67 66 10 15 20 25 30 35 40 45 50 55 60 fCLK (MHz)
74
10 15 20 25 30 35 40 45 50 55 60 fCLK (MHz)
TOTAL HARMONIC DISTORTION vs. SAMPLING RATE
MAX1438B toc16
SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
MAX1438B toc17
SIGNAL-TO-NOISE RATIO vs. DUTY CYCLE
fIN = 5.3037109MHz 72 71 SNR (dB) 70 69 68 67
MAX1438B toc18
-80 fIN = 5.3037109MHz -85 -90
115 fIN = 5.3037109MHz 110 105 SFDR (dBc) 100 95 90 85
73
THD (dBc)
-95 -100 -105 -110 10 15 20 25 30 35 40 45 50 55 60 fCLK (MHz)
10 15 20 25 30 35 40 45 50 55 60 fCLK (MHz)
30
35
40
45
50
55
60
65
70
DUTY CYCLE (%)
SIGNAL-TO-NOISE PLUS DISTORTION vs. DUTY CYCLE
MAX1438B toc19
TOTAL HARMONIC DISTORTION vs. DUTY CYCLE
MAX1438B toc20
SPURIOUS-FREE DYNAMIC RANGE vs. DUTY CYCLE
fIN = 5.3037109MHz 105 100 SFDR (dBc) 95 90 85 80
MAX1438B toc21
73 fIN = 5.3037109MHz 72 71 SINAD (dB)
-80 fIN = 5.3037109MHz -85 -90 THD (dBc) -95 -100 -105 -110
110
70 69 68 67 30 35 40 45 50 55 60 65 70 DUTY CYCLE (%)
30
35
40
45
50
55
60
65
70
30
35
40
45
50
55
60
65
70
DUTY CYCLE (%)
DUTY CYCLE (%)
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7
Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
Typical Operating Characteristics (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 64MHz (50% duty cycle), DT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
MAX1438B toc22
SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE
72 71 SINAD (dB) 70 69 68 67 66 65 THD (dBc) fIN = 19.8MHz 4096-POINT DATA RECORD
MAX1438B toc23
TOTAL HARMONIC DISTORTION vs. TEMPERATURE
-86 -87 -88 fIN = 19.8MHz 4096-POINT DATA RECORD
MAX1438B toc24
73 72 71 70 SNR (dB) 69 68 67 66 65
fIN = 19.8MHz 4096-POINT DATA RECORD
73
-85
-89 -90 -91 -92 -93 -94 -95
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
MAX1438B toc25
SUPPLY CURRENT vs. SAMPLING RATE (AVDD)
430 420 IOVDD (mA) IAVDD (mA) 410 400 390 380 370 360 65 0 5 10 15 20 25 30 35 40 45 50 55 60 fCLK (MHz) 80
MAX1438B toc26
SUPPLY CURRENT vs. SAMPLING RATE (OVDD)
MAX1438B toc27
95 94 93 92 SFDR (dBc) 91 90 89 88 87 86 85
fIN = 19.8MHz 4096-POINT DATA RECORD
440
90
85
75
70
-40
-15
10
35
60
85
0 5 10 15 20 25 30 35 40 45 50 55 60 fCLK (MHz)
TEMPERATURE (C)
OFFSET ERROR vs. TEMPERATURE
MAX1438B toc28
GAIN ERROR vs. TEMPERATURE
MAX1438B toc29
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4
MAX1438B toc30
0.03
0.2 0.0 GAIN ERROR (%FS) -0.2 -0.4 -0.6 -0.8
0.5
OFFSET ERROR (%FS)
0.02
0.01
0.00
-0.01 -40 -15 10 35 60 85 TEMPERATURE (C)
-1.0 -40 -15 10 35 60 85 TEMPERATURE (NC)
-0.5 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
8
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs
Typical Operating Characteristics (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 64MHz (50% duty cycle), DT = 0, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1438B toc31
MAX1438B
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1438B toc32
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
VAVDD = VOVDD 1.2600 VREFIO (V)
MAX1438B toc33
0.5 0.4 0.3 0.2 DNL (LSB)
1.2530 VAVDD = VOVDD 1.2520 VREFIO (V)
1.2700
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
1.2510
1.2500
1.2500
1.2400
1.2490 1.7 1.8 1.9 2.0 2.1 SUPPLY VOLTAGE (V)
1.2300 -40 -15 10 35 60 85 TEMPERATURE (NC)
INTERNAL REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT
MAX1438B toc34
CMOUT VOLTAGE vs. SUPPLY VOLTAGE
VAVDD = VOVDD 0.7790 VCMOUT (V)
MAX1438B toc35
1.4000 VAVDD = VOVDD 1.3500 1.3000 VREFIO(V) 1.2500 1.2000 1.1500 1.1000 -350 -250 -150 -50 50 150 250
0.7810
0.7770
0.7750
0.7730
0.7710 350 1.7 1.8 1.9 2.0 2.1 IREFIO (FA) SUPPLY VOLTAGE (V)
CMOUT VOLTAGE vs. TEMPERATURE
VAVDD = VOVDD 0.795 0.790 VCMOUT (V) 0.785 0.780 0.775 0.770 -40 -15 10 35 60 85 TEMPERATURE (NC)
MAX1438B toc36
CMOUT VOLTAGE vs. LOAD CURRENT
0.9 0.8 0.7 VCMOUT (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 500 1000 ICMOUT(FA) 1500 2000
MAX1438B toc37
0.800
1.0
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9
Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
Pin Description
PIN 1 2 3 4 5 6 7, 8, 10, 11, 25, 26, 27, 60 9, 18, 68 12 13 14 15 16 17 19 20 21 22 NAME IN1P IN1N IN2P IN2N IN3P IN3N AVDD GND IN4P IN4N IN5P IN5N IN6P IN6N IN7P IN7N DT SLVS/LVDS Channel 1 Positive Input Channel 1 Negative Input Channel 2 Positive Input Channel 2 Negative Input Channel 3 Positive Input Channel 3 Negative Input Analog Power Input. Connect AVDD to a 1.7V to 1.9V power supply. Bypass AVDD to GND with a 0.1F capacitor as close as possible to the device. Bypass the AVDD power plane to the GND plane with a bulk capacitor of at least 2.2F. Connect all AVDD pins to the same potential. Ground. Connect all GND pins to the same potential. Channel 4 Positive Input Channel 4 Negative Input Channel 5 Positive Input Channel 5 Negative Input Channel 6 Positive Input Channel 6 Negative Input Channel 7 Positive Input Channel 7 Negative Input Double Termination Select. Force DT high to select the internal 100 termination between the differential output pairs. Force DT low to select no internal output termination. Differential Output Signal Format Select Input. Force SLVS/LVDS high to select SLVS outputs. Force SLVS/LVDS low to select LVDS outputs. Clock Power Input. Connect CVDD to a 1.7V to 3.5V supply. Bypass CVDD to GND with a 0.1F capacitor in parallel with a capacitor of at least 2.2F. Install the bypass capacitors as close as possible to the device. CVDD is used to bias ESD-protection diodes on CLK (see Figure 2). Single-Ended CMOS Clock Input Output Driver Power Input. Connect OVDD to a 1.7V to 1.9V power supply. Bypass OVDD to GND with a 0.1F capacitor as close as possible to the device. Bypass the OVDD power plane to the GND plane with a bulk capacitor of at least 2.2F. Connect all OVDD pins to the same potential. Channel 7 Negative LVDS/SLVS Output Channel 7 Positive LVDS/SLVS Output Channel 6 Negative LVDS/SLVS Output Channel 6 Positive LVDS/SLVS Output Channel 5 Negative LVDS/SLVS Output Channel 5 Positive LVDS/SLVS Output Channel 4 Negative LVDS/SLVS Output Channel 4 Positive LVDS/SLVS Output Negative Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. Positive Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. Negative LVDS/SLVS Serial Clock Output FUNCTION
23 24 28, 31, 34, 39, 44, 49, 52 29 30 32 33 35 36 37 38 40 41 42
CVDD CLK OVDD OUT7N OUT7P OUT6N OUT6P OUT5N OUT5P OUT4N OUT4P FRAMEN FRAMEP CLKOUTN
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs
Pin Description (continued)
PIN 43 45 46 47 48 50 51 53 54 55 NAME CLKOUTP OUT3N OUT3P OUT2N OUT2P OUT1N OUT1P OUT0N OUT0P LVDSTEST Positive LVDS/SLVS Serial-Clock Output Channel 3 Negative LVDS/SLVS Output Channel 3 Positive LVDS/SLVS Output Channel 2 Negative LVDS/SLVS Output Channel 2 Positive LVDS/SLVS Output Channel 1 Negative LVDS/SLVS Output Channel 1 Positive LVDS/SLVS Output Channel 0 Negative LVDS/SLVS Output Channel 0 Positive LVDS/SLVS Output LVDS Test Pattern Enable. Force LVDSTEST high to enable the output test pattern, 0000 1011 1101. As with the analog conversion results, the test pattern data are output LSB first. Force LVDSTEST low for normal operation. Standby Input. Force STBY high to put the MAX1438B into standby mode. In standby, the reference circuitry remains active. Force STBY low for normal operation. PLL Control Input 3. See Table 1 for details. PLL Control Input 2. See Table 1 for details. PLL Control Input 1. See Table 1 for details. Negative Reference Bypass Output. Connect a capacitor of at least 1F (10F typ) between REFP and REFN, and connect a capacitor of at least 1F (10F typ) between REFN and GND. Place the capacitors as close as possible to the device on the same side of the PCB as the MAX1438B. Positive Reference Bypass Output. Connect a capacitor of at least 1F (10F typ) between REFP and REFN, and connect a capacitor of at least 1F (10F typical) between REFN and GND. Place the capacitors as close as possible to the device on the same side of the PCB as the MAX1438B. Reference Input/Output. For internal reference operation (REFADJ = GND), the reference output voltage is 1.24V. For external reference operation (REFADJ = AVDD), apply a stable reference voltage at REFIO. Bypass to GND with a capacitor of at least 0.1F. Internal/External Reference Mode Select and Reference Adjust Input. For internal reference, connect REFADJ to GND. For external reference, connect REFADJ to AVDD. For adjusting the reference, see the Full-Scale Range Adjustments Using the Internal Reference section. Common-Mode Reference Voltage Output. CMOUT outputs the input common-mode voltage for DC-coupled applications. Bypass CMOUT to GND with a capacitor of at least 0.1F. Channel 0 Positive Input Channel 0 Negative Input Exposed Pad. Internally connected to GND. Connect EP to a large ground plane for maximum thermal performance. Must be connected to GND. FUNCTION
MAX1438B
56 57 58 59 61
STBY PLL3 PLL2 PLL1 REFN
62
REFP
63
REFIO
64
REFADJ
65 66 67 --
CMOUT IN0P IN0N EP
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
Functional Diagram
REFADJ REFIO REFP REFN STBY AVDD OVDD DT SLVS/LVDS
CMOUT ICMV* IN0P T/H IN0N
REFERENCE SYSTEM
POWER CONTROL
MAX1438B
OUTPUT CONTROL
LVDSTEST
12-BIT PIPELINE ADC
12:1 SERIALIZER
OUT0P OUT0N
IN1P T/H IN1N
12-BIT PIPELINE ADC
12:1 SERIALIZER
OUT1P OUT1N
LVDS/SLVS OUTPUT DRIVERS IN7P IN7N T/H 12-BIT PIPELINE ADC 12:1 SERIALIZER OUT7P OUT7N FRAMEP FRAMEN CLOCK CIRCUITRY PLL 6x CLKOUTP CLKOUTN
CLK
CVDD
PLL1
PLL2
PLL3
GND
*ICMV = INPUT COMMON-MODE VOLTAGE (INTERNALLY GENERATED).
Detailed Description
The MAX1438B ADC features fully differential inputs, a pipelined architecture, and digital error correction for high-speed signal conversion. The ADC pipeline architecture moves the samples taken at the inputs through the pipeline stages every half clock cycle. The converted digital results are serialized and sent through the LVDS/SLVS output drivers. The total clock-cycle latency from input to output is 6.5 clock cycles. The MAX1438B offers 8 separate fully differential channels with synchronized inputs and outputs. Global standby minimizes power consumption.
Input Circuit
Figure 1 displays a simplified diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the operational transconductance amplifier (OTA), and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
SWITCHES SHOWN IN TRACK MODE INTERNALLY GENERATED COMMON-MODE LEVEL*
INTERNAL COMMON-MODE BIAS* AVDD
INTERNAL BIAS*
MAX1438B
S2a C1a
S5a
S3a S4a IN_P OUT S4c IN_N S4b C2b C1b S3b GND S2b INTERNAL COMMON-MODE BIAS* S5b S1 OTA OUT C2a
INTERNAL BIAS*
INTERNALLY GENERATED COMMON-MODE LEVEL*
*NOT EXTERNALLY ACCESSIBLE.
Figure 1. Internal Input Circuit
then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. Analog inputs, IN_P to IN_N, are driven differentially. For differential inputs, balance the input impedance of IN_P and IN_N for optimum performance.
Reference Configurations (REFIO, REFADJ, REFP, and REFN)
The MAX1438B provides an internal 1.24V bandgap reference or can be driven with an external reference voltage. The full-scale analog differential input range is FSR. FSR (full-scale range) is given by the following equation: FSR = (0.700 x VREFIO ) 1.24V
where VREFIO is the voltage at REFIO, generated internally or externally. For a VREFIO = 1.24V, the full-scale input range is 700mV (1.4VP-P).
Internal Reference Mode Connect REFADJ to GND to use the internal bandgap reference directly. The internal bandgap reference generates VREFIO to be 1.24V with a 120ppm/C temperature coefficient in internal reference mode. Connect an external 0.1F bypass capacitor from REFIO to GND for stability. REFIO sources up to 200A and sinks up to 200A for external circuits, and REFIO has a 75mV/mA load regulation. Putting the MAX1438B into standby mode turns off all circuitry except the reference circuit, allowing the converter to power up faster when the ADC exits standby with a high-to-low transitional signal on STBY. The internal circuits of the MAX1438B require 200s to power up and settle when the converter exits standby mode. To compensate for gain errors or to decrease or increase the ADC's FSR, add an external resistor between REFADJ and GND or REFADJ and REFIO. This adjusts the internal reference value of the MAX1438B by up to 5% of its nominal value. See the Full-Scale Range Adjustments Using the Internal Reference section.
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
Connect 1F (10F typ) capacitors to GND from REFP and REFN and a 1F (10F typ) capacitor between REFP and REFN as close as possible to the device on the same side of the PCB.
Table 1. PLL1, PLL2, and PLL3 Configuration Table
PLL1 0 0 0 0 1 1 1 1 PLL2 0 0 1 1 0 0 1 1 PLL3 0 1 0 1 0 1 0 1 INPUT CLOCK RANGE (MHz) MIN 45.0 32.5 22.5 16.3 11.3 8.1 5.6 4.0 MAX 64.0 45.0 32.5 22.5 16.3 11.3 8.1 5.6
External Reference Mode The external reference mode allows for more control over the MAX1438B reference voltage and allows multiple converters to use a common reference. Connect REFADJ to AVDD to disable the internal reference. Apply a stable 1.18V to 1.30V source at REFIO. Bypass REFIO to GND with a 0.1F capacitor. The REFIO input impedance is > 1M.
Clock Input (CLK)
The MAX1438B accepts a CMOS-compatible clock signal with a wide 20% to 80% input clock duty cycle. Drive CLK with an external single-ended clock signal. Figure 2 shows the simplified clock input diagram. Low clock jitter is required for the specified SNR performance of the MAX1438B. Analog input sampling occurs on the rising edge of CLK, requiring this edge to provide the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 x log 2 x x fIN x t J where fIN represents the analog input frequency and tJ is the total system clock jitter.
section). Set the PLL1, PLL2, and PLL3 pins according to the input clock range provided in Table 1.
System Timing Requirements
Figure 3 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data output. The differential analog input (IN_P and IN_N) is sampled on the rising edge of the CLK signal and the resulting data appears at the digital outputs 6.5 clock cycles later. Figure 4 provides a detailed, two-conversion timing diagram of the relationship between the inputs and the outputs.
PLL Inputs (PLL1, PLL2, PLL3) The MAX1438B features a PLL that generates an output clock signal with six times the frequency of the input clock. The output clock signal is used to clock data out of the MAX1438B (see the System Timing Requirements
Clock Output (CLKOUTP, CLKOUTN) The MAX1438B provides a differential clock output that consists of CLKOUTP and CLKOUTN. As shown in Figure 4, the serial output data is clocked out of the MAX1438B on both edges of the clock output. The frequency of the output clock is six times the frequency of CLK. Frame-Alignment Output (FRAMEP, FRAMEN) The MAX1438B provides a differential frame-alignment signal that consists of FRAMEP and FRAMEN. As shown in Figure 4, the rising edge of the frame-alignment signal corresponds to the first bit (D0) of the 12-bit serial data stream. The frequency of the framealignment signal is identical to the frequency of the input clock. Serial Output Data (OUT_P, OUT_N) The MAX1438B provides its conversion results through individual differential outputs consisting of OUT_P and OUT_N. The results are valid 6.5 input clock cycles after the sample is taken. As shown in Figure 3, the output data is clocked out on both edges of the output clock, LSB (D0) first. Figure 5 provides the detailed serial-output timing diagram.
AVDD
MAX1438B
CVDD DUTY-CYCLE EQUALIZER
CLK GND
Figure 2. Clock Input Circuitry
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
N+2 N (VIN_P VIN_N) N+1 tSAMPLE N+3 N+5 N+4 N+7 N+6 N+8 N+9
CLK
6.5 CLOCK-CYCLE DATA LATENCY
(VFRAMEP VFRAMEN)*
(VCLKOUTP VCLKOUTN)
(VOUT_P VOUT_N) OUTPUT DATA FOR SAMPLE N-6 *DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY. OUTPUT DATA FOR SAMPLE N
Figure 3. Global Timing Diagram
N+2 N (VIN_P - VIN_N) tSAMPLE CLK (VFRAMEP VFRAMEN)* (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) D5N-7 D6N-7 D7N-7 D8N-7 D9N-7 D10N-7 D11N-7 D0N-6 D1N-6 D2N-6 D3N-6 D4N-6 D5N-6 D6N-6 D7N-6 D8N-6 D9N-6 D10N-6 D11N-6 D0N-5 D1N-5 D2N-5 D3N-5 D4N-5 D5N-5 D6N-5 *DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY. N+1 tSF
tCF
Figure 4. Detailed Two-Conversion Timing Diagram
tCH (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) tCL
tOD D0 D1 D2
tOD D3
Figure 5. Serialized-Output Detailed Timing Diagram
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
Table 2. Output Code Table (VREFIO = 1.24V)
TWO'S-COMPLEMENT DIGITAL OUTPUT CODE BINARY D11 D0 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0001 1000 0000 0000 HEXADECIMAL EQUIVALENT OF D11 D0 0x7FF 0x7FE 0x001 0x000 0xFFF 0x801 0x800 DECIMAL EQUIVALENT OF D11 D0 +2047 +2046 +1 0 -1 -2047 -2048 VIN_P - VIN_N (mV) (VREFIO = 1.24V) +699.66 +699.32 +0.34 0 -0.34 -699.66 -700.00
1 LSB = 2 x FSR 4096 FSR TWO'S-COMPLEMENT OUTPUT CODE (LSB) 0x7FF 0x7FE 0x7FD
FSR = 700mV x VREFIO 1.24V FSR
0x001 0x000 0xFFF
0x803 0x802 0x801 0x800 -2047 -2045 -1 0 +1 +2045 +2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Two's-Complement Transfer Function
Output Data Transfer Function The MAX1438B output data format is two's complement. The following equation, Table 2, and Figure 6 define the relationship between the digital output and the analog input:
VIN _ P - VIN _ N = FSR x 2 x CODE10 4096
Keep the capacitive load on the MAX1438B digital outputs as low as possible.
LVDS and SLVS Selection (SLVS/LVDS)
Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high for SLVS levels at the MAX1438B outputs (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN). For SLVS levels, enable double-termination by driving DT high. See the Electrical Characteristics table for LVDS and SLVS output voltage levels.
where CODE10 is the decimal equivalent of the digital output code as shown in Table 2.
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs
LVDS Test Pattern (LVDSTEST)
Drive LVDSTEST high to enable the output test pattern on all LVDS or SLVS output channels. The output test pattern is 0000 1011 1101. Drive LVDSTEST low for normal operation (test pattern disabled).
DT
MAX1438B
Common-Mode Output (CMOUT)
CMOUT provides a common-mode reference for DCcoupled analog inputs. If the input is DC-coupled, match the output common-mode voltage of the circuit driving the MAX1438B to the output voltage at VCMOUT to within 50mV. It is recommended that the output common-mode voltage of the driving circuit be derived from CMOUT.
OUT_P/ CLKOUTP/ FRAMEP
Z0 = 50
100
100
Double Termination (DT)
The MAX1438B offers an optional, internal 100 termination between the differential output pairs (OUT_P and OUT_N, CLKOUTP and CLKOUTN, FRAMEP and FRAMEN). In addition to the termination at the end of the line, a second termination directly at the outputs helps eliminate unwanted reflections down the line. This feature is useful in applications where trace lengths are long (> 5in) or with mismatched impedance. Drive DT high to select double-termination, or drive DT low to disconnect the internal termination resistor (single-termination). Selecting double-termination increases the OVDD supply current (see Figure 7).
MAX1438B
OUT_N/ CLKOUTN/ FRAMEN
Z0 = 50
SWITCHES ARE CLOSED WHEN DT IS HIGH. SWITCHES ARE OPEN WHEN DT IS LOW.
Figure 7. Double Termination
the converter exits standby mode. To exit standby mode, STBY, the applied control signal must transition from high to low. When using an external reference, the wakeup time is dependent on the external reference drivers.
Standby Mode
The MAX1438B offers a standby mode to efficiently use power by transitioning to a low-power state when conversions are not required. STBY controls the standby mode of all channels and the internal reference circuitry. The reference does not power down in standby mode. Drive STBY high to enable standby. In standby mode, the output impedance of all of the LVDS/SLVS outputs is approximately 342, if DT is low. The output impedance of the differential LVDS/SLVS outputs is 100 when DT is high. See the Electrical Characteristics table for typical supply currents during standby. The following list shows the state of the analog inputs and digital outputs in standby mode: * IN_P, IN_N analog inputs are disconnected from the internal input amplifier. * * Reference circuit remains active. OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN have approximately 342 between the output pairs when DT is low. When DT is high, the differential output pairs have 100 between each pair.
Applications Information
Full-Scale Range Adjustments Using the Internal Reference
The MAX1438B supports a full-scale adjustment range of 10% (5%). To decrease the full-scale range, add a 25k to 250k external resistor or potentiometer (RADJ) between REFADJ and GND. To increase the full-scale range, add a 25k to 250k resistor between REFADJ and REFIO. Figure 8 shows the two possible configurations. The following equations provide the relationship between RADJ and the change in the analog full-scale range: 1.25k FSR = 0.7V 1 + RADJ for RADJ connected between REFADJ and REFIO, and: 1.25k FSR = 0.7V 1 - RADJ for RADJ connected between REFADJ and GND.
When operating in internal reference mode, the MAX1438B requires 200s to power up and settle when
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
10 ADC FULL-SCALE = REFT - REFB REFERENCESCALING AMPLIFIER VIN N.C. 0.1F 1 T1 2 5 0.1F 3 4 MINICIRCUITS ADT1-1WT 25k TO 250k 6 39pF IN_P
REFT REFB REFERENCE BUFFER
G
MAX1438B
REFIO 1V REFADJ CONTROL LINE TO DISABLE REFERENCE BUFFER
0.1F
10 IN_N 39pF
Figure 9. Transformer-Coupled Input Drive
25k TO 250k
MAX1438B
AVCC
AVCC/2
the MAX1438B ground pins and the exposed backside pad to the same ground plane. The MAX1438B relies on the exposed-backside-pad connection for a lowinductance ground connection. Isolate the ground plane from any noisy digital system ground planes. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90 turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1438B EV kit data sheet for an example of symmetric input layout.
Figure 8. Circuit Suggestions to Adjust the ADC's Full-Scale Range
Using Transformer Coupling
An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal. The MAX1438B input common-mode voltage is internally biased to 0.76V (typ) with f CLK = 64MHz. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion.
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer function from a straight line. For the MAX1438B, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table.
Grounding, Bypassing, and Board Layout
The MAX1438B requires high-speed board layout design techniques. Refer to the MAX1438B EV kit data sheet for a board layout reference. Locate all bypass capacitors as close as possible to the device, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass AVDD to GND with a 0.1F ceramic capacitor in parallel with a 0.1F ceramic capacitor. Bypass OVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Bypass CVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. Connect
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1438B, DNL deviations are measured at every step and the worstcase deviation is reported in the Electrical Characteristics table.
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs
Offset Error
Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. For the MAX1438B, the ideal midscale digital output transition occurs when there is -1/2 LSBs across the analog inputs (Figure 6). Bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.
CLK tAD ANALOG INPUT tAJ SAMPLED DATA
MAX1438B
Gain Error
Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1438B, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. For the bipolar device (MAX1438B), the full-scale transition point is from 0x7FE to 0x7FF and the zero-scale transition point is from 0x800 to 0x801.
T/H HOLD TRACK HOLD
Figure 10. Aperture Jitter/Delay Specifications
includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2-HD7), and the DC offset.
Crosstalk
Crosstalk indicates how well each analog input is isolated from the others. For the MAX1438B, a 5.3MHz, -0.5dBFS analog signal is applied to 1 channel while a 30.3MHz, -0.5dBFS analog signal is applied to another channel. An FFT is taken on the channel with the 5.3MHz analog signal. From this FFT, the crosstalk is measured as the difference in the 5.3MHz and 30.3MHz amplitudes.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency, excluding the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD - 1.76 ENOB = 6.02
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. See Figure 10.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay. See Figure 10.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: V 2+V 2+V 2+V 2+V 2+V 2 3 4 5 6 7 THD = 20 x log 2 V1
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. For the MAX1438B, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc).
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs MAX1438B
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6.5dBFS. The intermodulation products are as follows: * 2nd-order intermodulation products (IM2): f1 + f2, f2 - f1 * * * 3rd-order intermodulation products (IM3): 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1 4th-order intermodulation products (IM4): 3 x f1 - f2, 3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1 5th-order intermodulation products (IM5): 3 x f1 - 2 x f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Gain Matching
Gain matching is a figure of merit that indicates how well the gain of all 8 ADC channels is matched to each other. For the MAX1438B, gain matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 64Msps and the maximum deviation in amplitude is reported in dB as gain matching in the Electrical Characteristics table.
Third-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6.5dBFS. The 3rd-order intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1.
Phase Matching
Phase matching is a figure of merit that indicates how well the phases of all 8 ADC channels are matched to each other. For the MAX1438B, phase matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 64Msps and the maximum deviation in phase is reported in degrees as phase matching in the Electrical Characteristics table.
Small-Signal Bandwidth
A small -20.5dBFS analog input signal is applied to an ADC so that the signal's slew rate does not limit the ADC's performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB.
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Octal, 12-Bit, 64Msps, 1.8V ADC with Serial LVDS Outputs
Pin Configuration
TOP VIEW PLL2 PLL3 STBY LVDSTEST CMOUT REFADJ REFIO REFP REFN AVDD PLL1 OUT0P OUT0N OVDD
MAX1438B
IN1P IN1N IN2P IN2N IN3P IN3N AVDD AVDD GND AVDD
GND
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 1 2 3 4 5 6 7 8 9 10 51
IN0N IN0P
+
50 49 48 47 46 45
OUT1P OUT1N OVDD OUT2P OUT2N OUT3P OUT3N OVDD CLKOUTP CLKOUTN FRAMEP FRAMEN OVDD OUT4P OUT4N OUT5P OUT5N
MAX1438B
44 43 42 41 40 39 38
AVDD 11 IN4P 12 IN4N 13 IN5P IN5N IN6P IN6N
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
EXPOSED PAD. CONNECTED TO GND.
37 36 35
AVDD AVDD OVDD OUT7N OUT7P OVDD OUT6N
OUT6P
IN7P IN7N DT SLVS/LVDS CVDD CLK
TQFN (10mm x 10mm x 0.8mm)
OVDD
GND
AVDD
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 68 TQFN-EP PACKAGE CODE T6800-4 DOCUMENT NO. 21-0142
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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